In this article we will discuss about combinational and sequential circuits and their functions.

Introduction to Combinational and Sequential Circuits:

A digital system must store binary numbers in addition to performing logic. To take care of this requirement, a memory cell, called a FLIP-FLOP, is introduced. Theoretically any digital system can be constructed entirely from NAND gates and FLIP-FLOPs. These integrated circuits form the practical (commercially available) basic building blocks for a digital system.

These chips perform the following functions:

1. Binary addition;


2. Decoding (demultiplexing);

3. Data selection (multiplexing);

4. Counting;

5. Storage of binary information (memories and registers);


6. D/A and A/D conversion; and

7. A few other related operations.

Those building blocks depend upon combinational logic. The standard combinations are small- scale integration (SSI). Less than 100 individual circuit components (about 12 gates) on a chip are considered SSI. The flip-flops are also SSI packages. Most other functions (using BJTs) are examples of medium scale integration (MSI), defined to have more than 100 but less than 1000 components (about 100 gates per chip). The BJT memories and MOSFET arrays may contain in excess of 1000 components and are defined as large scale integration (LSI).

SSI < 100 individual circuits (about 12 gates) – (e.g., flip-flop).


MSI > 100 but < 1000 (about 100 gates) – (e.g., most circuit using BJT).

LSI > 1000 – (e.g., BJT memories and MOSFET arrays).

Binary Addition:

It is the basic operation. Multiplication can be obtained by programming.

A two-input adder is called a half adder, because to complete an addition requires two such half adders.


Half Adder:

A half adder has two inputs A and B representing the bits to be added and two outputs D and C, where D is for the digit of the same significance as A and B represent and C for the carry bit. Parallel operation of binary adder is illustrated in Fig. 6.2.

Full Adder:


The symbol for the n-th hill adder (FA) is shown in Fig. 6.3(a). The circuit has three inputs: the addend An, the augend Bn and the input carry Cn-1 (from the next lower bit). The output is the sum Sn and the output carry Cn.

A parallel 4-bit adder is shown in Fig. 6.3(b). As FAO represents the least significant bit (LSB), it has no input carry; hence Cn = 0.

The circuitry within the block FA is determined from Fig. 6.4, which is the truth table for adding 3 binary bits.

From this table one can verify that the Boolean expressions for Sn and Cn are given by-

It may be noted that the first term of Sn corresponds to line 1 of the table, the second term to line 2, the third term to line 4 and the last term to line 7 (these are the only rows where Sn = 1). In a similar way the first term of Cn corresponds to line 3 (where Cn = 1), the second term to line 5, etc.

The AND operation ABC is also called the product of A, B and C. Further, the OR operation + is referred to as summation. So expressions shown in equations (6.1) and (6.2) represent a Boolean sum of products. Such an equation is said to be in a standard, or canonical form and each term in the equation is called a minterm which contains the product of all Boolean variables or their components. Only one full adder is required for serial arithmetic, while in parallel addition we must use a full adder for each bit. Thus, parallel addition becomes more expensive than serial operation.

A serial binary full adder is indicated in Fig. 6.5. The time delay unit TD is a type D FLIP- FLOP and the serial numbers An, Bn and Sn are stored in shift registers.


In a digital system, instructions as well as numbers are conveyed by using binary levels or pulse trains. If 4 bits of a character are set aside to convey instructions, then 16 different instructions are possible. This information is coded in binary form.

Frequently a need arises for a multiposition switch which is operated in accordance with this code. It means that for each of the 16 codes, one and only one line is to be excited. This process of identifying a particular code is known as decoding.

Binary-Coded-Decimal (BCD) System:

The code translates decimal numbers by replacing each decimal digit with a combination of 4 binary digits. As there are 16 distinct ways in which the 4 binary digits can be arranged in a row, any 10 combinations can be used to represent the decimal digits from 0 to 9. In fact, we have a wide choice of BCD codes. One of these, called the “natural binary-coded decimal” is the 8421 code. This is illustrated in Table 6.1.

This is a weighted code as the decimal digit in 8421 code is equal to the sum of the products of the bits in the coded words times the successive powers of two starting from the right (LSB). We require N 4-bit sets to represent in BCD notation as N-digit decimal number. The first 4-bit set on the right represents units, the second represents tens, the third hundreds and so on.

For example, the decimal number 264 requires three 4-bit sets, as shown in Table 6.2. This three-decade BCD code can represent any number between 0 and 999. Thus, it has a resolution of 1 part in 1000 or 0.1%. It needs 12 bits which in a straight binary code can resolve one part in 212 = 4096 or 0.025%.

BCD-to-Decimal Decoder:

Let we like to decode a BCD instruction representing one decimal digit, say 5. The operation is carried out with a four-input AND gate excited by the 4 BCD bits. The output of the AND gate in Fig. 6.6 is I, if and only if the BCD inputs are A = 1 (LSB), B = 0, C = 1 and D = 0. As this code represents the decimal number 5, the output is labelled “line 5”.

A BCD-to-decimal decoder is shown in Fig. 6.7. The MSI unit has four inputs, A, B, C and D and ten output lines. Moreover, there must be a ground and a power supply connection and so a 16-pin package 5 is needed. The complementary inputs A, B, C and D are found from inverters on the chip.

As NAND gates are used, output is 0 (low) for the correct BCD code and is 1 (high) for any other invalid code. The system shown in Fig. 6.7 is also referred to as a “4-to-10-line decoder” designating that a 4-bit input code selects 1 of 10 output lines. Thus, the decoder works as a 10-position switch which responds to a BCD input instruction.

It is required to decode only during certain intervals of time. In such applications an additional input, known as a strobe, is added to each NAND gate. All strobe inputs are tied together and are excited by a binary signal S. This is shown by the dashed lines in Fig. 6.7. If S = 1, a gate is enabled and decoding takes place, while if S = 0, no coincidence is possible and decoding is inhibited. The strobe input is used with a decoder having any number of inputs or outputs.

[Multiplexer (Data Selector):

The function performed by a multiplexer is to select 1 out of N input data sources and thereby to transmit the selected data to a single information channel.


A decoder is a system which accepts an M- bit word and establishes the state 1 on one and only one of 2M output lines. A decoder thus identifies a particular code. The inverse process is known as encoding. An encoder has a number of inputs, only one of which is in the 1 state. An N-bit code is generated in an encoder depending upon which of the inputs is excited.

We consider that a binary code is transmitted with every stroke of an alphanumeric keyboard. There are 26 lower case and 26 capital letters, 10 numerals and about 22 special characters on a keyboard. Thus, the total number of codes necessary is approximately 84. This condition is satisfied with a minimum of 7 bits (27 = 128, but 26 = 64).

Let us assume that the keyboard is modified so that if a key is depressed, a switch is closed, hence connecting a 5-V supply corresponding to the 1 state to an input line. A block diagram of an encoder is shown in Fig. 6.8. Inside the shaded block there is a rectangular array of wires and we determine how to interconnect these wires so as to generate the desired codes.

In order to explain the design procedure for constructing an encoder, we simplify the above example by limiting the keyboard to only 10 keys, the numerals 0, 1, …, 9. A 4-bit output code is sufficient in this case and we choose BCD words for the output codes. The truth table defining this encoding is given in Table 6.3.

Input Wn (n = 0, 1,…, 9) indicates the n-th key. When Wn = 1, key n is depressed. As it is considered that not more than one key is activated simultaneously, then in any row every input except 1 is a 0. From this truth table we find that Y0 = 1, if W1 = 1, W3 = 1, W5 = 1, W7 = 1, W9 = 1.

Thus, in Boolean notation,

The OR gates in equations 6.3 and 6.4 are implemented in the form of array and is known as a rectangular diode matrix.

Read Only Memory (ROM):

Let us consider the problem of converting one binary code into another. Such a code-conversion system is known as ROM [Fig. 6.9(a)]. It has M inputs (X0, X1,…, XM-1,) and N outputs (Y0, Y1,…, YN-1), where N may be greater than, equal to or less than M. A definite M-bit code is to result in a specific output code of N bits.

The code translation is obtained by first decoding the M inputs onto 2M = µ word lines (W0, W1 …, W1-µ) and then encoding each line into the desired output word. If the inputs assume all possible combinations of 1s and 0s, then µ N-bit words are “read” at the output.

The functional relationship between output and input words is built into hardware in the encoder block of Fig. 6.9. As this information is stored permanently, we may say that the system has “memory”. The memory elements are the diodes or the emitters of transistors.

The output word for any input code may be read as often as desired. As the stored relationship between output and input codes cannot be modified without adding or subtracting memory elements (hardware), this system is termed a read only memory and abbreviated as ROM.

A typical bipolar ROM (MM 6280) is available from monolithic M = 210 = 1024 words of 8 bits each. This size is referred to as an 8 x 1024 = 8192-bit memory. This is a good example of a large scale integration (LSI).

Random Access Memory (RAM):

The random access memory, abbreviated as RAM, is an array of storage cells that memorize information in binary form. In this memory, information can be randomly written into or read out of each storage element as needed and hence it is called as the random access or read/write memory.

Linear Selection:

In order to explain how the RAM operates we consider 1-bit S-R FLIP- FLOP circuit shown in Fig. 6.10, with data input and output lines. From the figure we find that to read data out of or to write data into the cell, it is required to excite the address line (X = 1). To perform the write operation, the write enable line must be excited. If the write input is a logic 1 (0), then S = 1 (0) and R = 0 (1). Hence Q = 1 (0) and the data read out is 1 (0), corresponding to that written in.

Let us assume that we like to read/write 16 words of 8 bits each. This system needs eight data inputs and eight data outputs lines. A total of 16 x 8 = 128 storage cells must be used. Of this number, 8 cells are arranged in a horizontal line, all excited by the same address line. There are 16 such lines, each excited by a different address. This means that addressing is provided by exciting 1 of 16 lines. This type of addressing is known as linear selection.

Coincident Selection:

An RAM memory of sixteen 8-bit words has 16 lines with 8-storage cells per line, when linear addressing is used. A commonly used topology is to arrange 16 memory elements in a rectangular 4 x 4 array, each cell now storing one bit of one word. Bight such matrix planes are necessary, one for each of the 8 bits in each word.

One plane of the arrangement of cells is indicated in Fig. 6.11. Each bit as indicated as a shaded rectangle, is located by addressing an X-address line and a Y- address line; the intersection of the two lines locates a point in the two-dimensional matrix and thus identifies the storage cell under consideration. This two-dimensional addressing is known as X-Y or coincident selection.

Basic RAM Elements:

In the 1-bit memory of Fig. 6.10 separate read and write leads are essential. For either the bipolar or the MOS RAM it is possible to construct a FLIP-FLOP which has a common terminal for both writing and reading, such as terminals 1 and 2 in Fig. 6.12. This configuration needs the use not only on the write data W (write 1) but also of its complement W (write 0). At the cell terminal to which W (W) is applied, there is achieved the read or sense data output S (S). Such a memory unit is indicated in Fig. 6.12.

Here a total of four input/output leads to the storage cell is required, two for X-Y addressing and two for read/write data necessary. The base elements on which an RAM is constructed are shown in Fig. 6.13. These include the rectangular array of storage cells, the X and Y decoders, the write amplifiers to drive the memory and also the sense amplifiers to detect the stored digital information.

Some RAMs include a write enable input, wherein the write amplifiers of Fig. 6.13 are two input AND gates as in Fig. 6.12. Each word is identified by the matrix number X-Y in the (shaded) memory cell. For M-bit words there will be M planes, as in Fig. 6.13. Since in Fig. 6.12 the output of the write amplifier is connected to the input of the read amplifier, indicating that the sense amplifiers must not be used to supply information on the state of a memory cell when a write amplifier is excited.

An example of a 16-bit bipolar RAM of the pattern of Fig. 6.13 is the TI 7481. Average power dissipation is 275 mW and reading propagation delay is typically 20 ns. A larger RAM is the IM 5503 (Intersil Memory Corporation) having 16 x 16 = 256 words by 1-bit organization and has an excess time of 75 ns.


Fig. 6.14 shows a three-input, direct-coupled transistor logic (DCTL) NOR gate. The name direct-coupled comes from the fact that the inputs are coupled directly to the transistor bases.

A 1 input on A or B or C will turn on the transistor whose base has the 1 on it (assuming positive logic). This will cause the output to be low or a 0. When all inputs are zero, all three transistors will be OFF and the output will be a 1. In fact, as we know that this is the condition for a NOR gate.

DCTL gates are susceptible to what is called “current hogging”. Let the circuit in Fig. 6.14 is loaded with several other DCTL NOR gates. This means that several base-emitter junctions are being driven from the same point and due to inevitable differences in their base-to-emitter characteristics, one junction will turn on first. It is quite possible for the first junction to “hog” sufficient current to prevent some of the other junctions from turning ON.


The problem of current hogging can be easily solved by placing a resistor in series with each input base. The result is the resistor-transistor logic (RTL) NOR circuit. The current hogging is avoided as the resistors isolate the bases from the common driving point, thereby permitting the base-emitter voltages to individually adjust to the levels necessary for turn-ON. The addition of the input series resistors also increases the circuit input impedance, so that the fan-out of the driving circuit is increased.

RTL circuits were the first type of logic to be integrated in the early 1960s. The basic circuit had been proved in discrete-circuit form and was readily adaptable to integrated circuit fabrication. Thus, designers were familiar with RTL and lots of reliability and evaluation data were available.

RTL circuits have three main disadvantages:

(i) Relatively low speed,

(ii) Low fan-out and

(iii) Temperature sensitivity.

The low speed arises because the external series base resistor combines with the input capacity of the transistor to form a low-pass filter. This degrades the rise and fall times of any input pulse.

The low fan-out occurs as the input current to a given transistor is limited by having to flow through RL and the series base resistor of the next gate.


Speed in RTL circuits is a function of the size of the resistors used, since inherent transistor and stray capacities must be charged and discharged through collector and base resistors. In order to increase speed, resistors can be reduced in value but this increases the circuit power requirements.

To achieve high speed with less power, RTL circuits can be modified to the RCTL (resistor- capacitor-transistor logic). Here, the base resistors have been paralleled by speed-up capacitors, so that fast rise and fall can be achieved, even with relatively large base resistors. Apart from a high ratio of speed to power, RCTL is not significantly different from RTL and has not become widely accepted.


Another type of logic which was very popular as a discrete circuit and which was quickly translated into integrated form is DTL (diode-transistor logic).

As shown in Fig. 6.17, this usually consists of an input-diode AND gate (D1, D2, D3 and D4) followed by a transistor inverter which results in a NOT-AND or NAND gate. If any of the inputs A, B, C and D are low (a logic 0), point X will be approximately +0.7 V and the transistor will be turned OFF because its VBE will be less than 0.7 owing to D5 and D6. The output is, therefore, high (a logic 1).

However, if inputs A, B, C and D are all high (logic 1), all of the four input diodes turn OFF and the values of the two base bias resistors are such that the transistor turns ON. Its output is, therefore, low (a logic 0) only when all inputs are high (1). This is, in fact, the condition for a NAND gate.

The two extra diodes, D5 and D6, serve two purposes. With any input low they cause the base of the transistor to be well below +0.7 V, which ensures that the transistor is solidly off. Also, all inputs must rise above + 1.4 V before the transistor can turn ON, because point X in the figure is three diode drops (D5, D6 and the transistor base emitter) or 3 x 0.7 V = 2.1 V above ground as the transistor turns ON.

DTL is well-suited to monolithic integrated circuit fabrication. No capacitors are required and component values are not critical. Also, some monolithic versions of the DTL NAND gate in Fig. 6.4 replace D5 with a transistor. This improves performance. Replacing a diode with a transistor in a monolithic circuit would improve performance.


A form of logic that is related to DTL is shown in Fig. 6.18(a). It is called transistor-transistor logic, and abbreviated as TTL or T2L.

In the DTL circuit of Fig. 6.17, D4 and D5 form an np-pn combination. In TTL this combination is replaced with an npn transistor. To get multiple-input AND gate similar to the four-diode AND gate in the DTL circuit, TTL circuit uses multiple emitters on the npn transistor.

The logic action of the TTL ckt can be understood comparing the explanation for the DTL circuit. TTL is an example of the application of monolithic integrated circuit technology. When a DTL circuit is integrated, it cannot take advantage of the technique in the same way as TTL can.

Since the multiemitter transistor is smaller in area than the number of diodes it replaces, the yield from a wafer is improved. Moreover, the smaller area results in a lower capacitance to the substrate, thus, reducing circuit rise and fall times and increasing speed. Fig. 6.18(b) shows how a TTL NAND gate might be integrated.

The TTL circuit of Fig. 6.18(a) is practically not used in its basic form due to its limited noise immunity. The higher speeds and fan-out are possible with a modified version as shown in Fig. 6.18(c).

TTL input circuits need higher drive currents than DTL. This is why TTL circuits usually have high-power output stages. The output circuit in Fig. 6.18(c) is called a totem-pole output, as the three output components Q3, D1 and Q4 are stacked one on top of another in the manner of a totem-pole.

Other Integrated Circuit Subsystems:

The more common (non-memory) digital subsystems which are made up of combinations.

Medium scale integrated circuits (MSI) are introduced here as many of these subsystems are available on a single chip of silicon.


One of the functions frequently required in digital system is the ability to count. Such counting is not done in the decimal system but in binary system of 1s and 0s. The simplest type of counter is the binary ripple counter which contains three cascaded flip-flops, with the output of each flip- flop triggering the next, with a total count capacity of 0 to 7.

There are many variations of this basic binary counter. The maximum count can be extended to 15, by adding one more flip-flop.

The total number of allowed states is called as the modulus of the counter. For example, one that is capable of counts 0, 1, 2, 3, 4, 5, 6 and 7 is a mod-8 counter as in Fig. 6.19. A similar counter with one disallowed state (say, it skips 2) is a mod-7 counter.

The decade counter has a base or modulus of 10. The binary counter of Fig. 6.19 can be converted to a decade counter by adding one more flip-flop and eliminating 6 of the 16 possible states. One method of eliminating states is to leave off the last 6 counts so that the remaining 10 counts have the same weighting as the binary counter of Fig. 6.19.

Considering the waveforms and truth table of Fig. 6.20, we find that to limit the binary counter to a total of 10 counts we have to stop at the count of 9 instead of advancing to 10.

The status of the flip-flops at the counts of 9 and 10 would normally be-

If we return the counter to 0 after the count of 9, we have to do the following:

1. Prevent flip-flop B from setting to 1.

2. Reset D to 0.

A decade counter is similar to the binary counter of Fig. 6.19, but it has the extra stage, like the master-slave RST flip-flop, and the interconnection changes are made to stop the count at 9.

Considering Fig. 6.20(a) the operation of the decade counter can be explained as follows. When the counter attains 9, that is-

QD = 0 and this is fed back to the set input of flip-flop B. As flip-flop B is 0, the first requirement is satisfied. At the count of 9, QB = 1 and QC = 1, and the NOR gate output becomes 0. The NOR gate is connected to the set input of flip-flop D. As RD is normally high, flip-flop D is reset to 0 after the count of 9.

The waveforms of Fig. 6.20(b) illustrate the inherent frequency division capability of digital counters. Thus, the input or clock frequency is divided in half at each successive flip-flop.

Fig. 6.21 is an example of a digital circuit. The decoded output of a single Decade Counter Unit (DCU) represents only one decimal digit (varying from 0 through 9); therefore, additional DCU stages must be cascaded to increase the capacity to numbers greater than 9, i.e., tens and hundreds.

A typical three-digit DCU capable of counting to 999 is shown in Fig. 6.21. Note that a carry line connects the highest order BCD output of each DCU to each succeeding higher power DCU. The carry is necessary to advance the count from one power to the next; i.e., after the units DCU has progressed through the count of 9, the tens DCU must start at 0001.

Shift Registers:

Its circuit is similar to that of the multiple flip-flop counters of Figs. 6.19 and 6.20, but its function is somewhat different. Registers are a very important part of most digital systems. They are used to temporarily store binary information, especially before or after conversion or encoding/decoding operations. They allow a simple means of converting from serial to parallel (or vice versa) format.

Registers are also fundamental to the basic arithmetic operations such as multiplication, division, complementation and analogue-to-digital (and vice versa) conversion. Since, a flip-flop can store only one binary number (1 or 0), a shift register must contain one flip- flop for each bit of a binary number. There must also be some provision for entering (shifting) the binary number into, out of, and from one stage to another of the shift register. This brings up the two general methods of shifting data into shift registers, serial and parallel.

The first involves serially shifting one bit at a time into the register, whereas all the data are entered at the same time in a parallel shift register. The more universal MSI shift registers have designed so that data can be entered serially or in parallel so that the register can be used for a variety of sequential operations.

Fig. 6.22 demonstrates the basic serial shift-register technique. This is a four-stage (four-bit) serial shift register. Note that each Q output is directly coupled to the/input of the adjacent flip- flop, and the triggering inputs are all in parallel to provide simultaneous shifting of data from A to B, etc.

After all flip-flops are initially reset to 0, the/and K inputs of the first flip-flop (A) determine whether a 1 or a 0 is inserted into the register. At each clock pulse the state (Q = 0 or 1) of flip-flop A is shifted to the next higher order stage (B) and so on until the four-bit word is entered in the register. Four more clock pulses will then shift the word completely out of the register.

Digital-to-Analogue and Analogue-to-Digital Conversion:

We shall now discuss the important operations of digital-to-analogue (D/A) and analogue-to- digital (A/D) conversion. The best examples of D/A include conversion from binary machine language to analogue signals for plotters, recorders or meters. A/D conversion is often needed to convert analogue transducer outputs to digital form for input into a digital system.

D/A conversion is much simpler than A/D conversion and in fact a D/A converter is usually included as part of an A/D converter. For this reason, we shall discuss D/A conversion first. The basic problem in D/A conversion is to change a string of digital 0s and 1s to an equivalent analogue voltage. For example, consider the binary numbers 0 through 9 and the equivalent weighted analogue voltages shown in Fig. 6.23(a).

In this case we have made an arbitrary decision that the maximum analogue voltage is 9 V. Since there are 10 different decimal equivalents to express, the lowest (0000) is made equal to 0V and the highest (1001) to 9V, with 1V increments. Therefore, each binary number is expressed as a discrete analogue voltage. Note that, as we progress from one bit to the next, the equivalent analogue voltage doubles; i.e., 21 = 2 V, 22 = 4 V, 23 = 8 V.

A resistive divider and operational amplifier [Fig. 6.23(b)] is all that is needed to perform the D/A conversion indicated in Fig. 6.23(a). Note the common output summing point and the fact that the weighted resistor values decrease by a factor of 2 for each bit increase. This means that with a high 23 input the current through R/8 is twice that through R/4 with a high 22 input. Hence, the network fulfills the requirement of doubling the analogue current or voltage for every succeeding bit.

There is more hardware involved in an actual D/A converter than just the precision resistive divider. Fig. 6.24 shows a block diagram of a typical D/A converter.

Proceeding from the parallel digital input, we see that some form of storage is required for the digital information, plus some means of inputs controlling the data read-in and read-out. Next, level amplifiers and a precision voltage reference are needed to ensure that the normally imprecise digital signals are equal and constant, regardless of environmental or ladder loading effects.

These amplifiers operate in the analogue comparator mode, i.e., they have two inputs- the reference voltage and one of the shift-register outputs. Hence the output of a particular level amplifier is either low or high (≈0 or equal to the reference voltage), depending on the state of its input from the shift register. Thus, the resistive divider is provided with the proper digital inputs and it performs the actual digital-to-analogue conversion.

A/D Converter:

In this system a continuous sequence of equally spaced pulses is passed through a gate. The gate is normally closed and is opened at the instant of the beginning of a linear ramp.

The A/D converter using a counter is shown in Fig. 6.25(a) while the counter ramp waveform is shown in Fig. 6.25(b).

In Fig. 6.25(a), the clear pulse resets the counter to the zero count. In binary form the number of pulses are then recorded by the counter from the clock line. The clock is nothing but a source of pulses equally spaced in time. The binary word representing this count is used as the input of a D/A converter whose output is represented in Fig. 6.25(b).

So long input Vs is greater than Vd, the comparator output is high and the AND gate is open for the transmission of the clock pulses to the counter. When Vd becomes greater than Vs, the output of the comparator changes to the low value and then the AND gate is disabled. This stops the counting at the moment when Vs ≈ Vd. The count can be read out as the digital word represents the analogue input voltage.